IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 96 / 146

IDT Configuration Registers
PES12T3G2 User Manual 8 - 20 January 28, 2013
Notes
PCIEDCAP - PCI Express Device Capabilities (0x044)
24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express link asso-
ciated with this Port is connected to a slot. This field does not apply
to an upstream port and should be set to zero.
29:25 IMN RO 0x0 Interrupt Message Number. The function is allocated none
(upstream ports) or only one (downstream ports) MSI. Therefore,
this field is set to zero.
31:30 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
2:0 MPAYLOAD RWL HWINIT Maximum Payload Size Supported. This field indicates the
maximum payload size that the device can support for TLPs.
For all bond options the default value is 0x4 which corresponds to
2048 bytes.
4:3 PFS RO 0x0 Phantom Functions Supported. This field indicates the support
for unclaimed function number to extend the number of outstand-
ing transactions allowed by logically combining unclaimed func-
tion numbers. The value is hardwired to 0x0 to indicate that no
function number bits are used for phantom functions.
5 ETAG RWL 0x1 Extended Tag Field Support. This field indicates the maximum
supported size of the Tag field as a requester.
8:6 E0AL RO 0x0 Endpoint L0s Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due to
transition from the L0s state to the L0 state. The value is hard-
wired to 0x0 as this field does not apply to a switch.
11:9 E1AL RO 0x0 Endpoint L1 Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due to
transition from the L1 state to the L0 state. The value is hardwired
to 0x0 as this field does not apply to a switch.
12 ABP RO 0x0 Attention Button Present. In PCIe base 1.0a when set, this bit
indicates that an Attention Button is implemented on the card/
module.
The value of this field is undefined in PCIe base 1.1
13 AIP RO 0x0 Attention Indicator Present. In PCIe base 1.0a when set, this bit
indicates that an Attention Indicator is implemented on the card/
module.
The value of this field is undefined in PCIe base 1.1
14 PIP RO 0x0 Power Indicator Present. In PCIe base 1.0a when set, this bit
indicates that a Power Indicator is implemented on the card/mod-
ule.
The value of this field is undefined in PCIe base 1.1
15 RBERR RO 0x1 Role Based Error Reporting. This bit is set to indicate that the
PES12T3G2 supports error reporting as defined in the PCIe base
1.1 specification.
17:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description