IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT JTAG Boundary Scan
PES12T3G2 User Manual 9 - 3 January 28, 2013
Notes
Boundary Scan Chain
Test Data Register (DR)
The Test Data register contains the following:

Bypass register

Boundary Scan registers
Function Pin Name Type
1
1.
I = Input, O = Output
Boundary Cell
2
2.
O = Observe, C = Control
PCI Express Interface PE0RN[3:0] I O
PE0RP[3:0] I O
PE0TN[3:0] O C
PE0TP[3:0] O
PE2RN[3:0] I O
PE2RP[3:0] I O
PE2TN[3:0] O C
PE2TP[3:0] O
PE4RN[3:0] I O
PE4RP[3:0] I O
PE4TN[3:0] O C
PE4TP[3:0] O
PEREFCLKN[0] I —
PEREFCLKP[0] I —
REFCLKM I O
SMBus MSMBADDR[4:1] I O
MSMBCLK I/O O/C
MSMBDAT I/O O/C
SSMBADDR[5,3:1] I O
SSMBCLK I/O O/C
SSMBDAT I/O O/C
General Purpose I/O GPIO[11,7:0] I/O O/C
System Pins CCLKDS I O
CCLKUS I O
MSMBSMODE I O
PERSTN I O
RSTHALT I O
SWMODE[2:0] I —
EJTAG / JTAG JTAG_TCK I —
JTAG_TDI I —
JTAG_TDO O —
JTAG_TMS I —
JTAG_TRST_N I —
Table 9.2 Boundary Scan Chain