IDT 89HPES12T3G2, Preliminary User'S Manual

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Notes
PES12T3G2 User Manual 5 - 1 January 28, 2013
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Chapter 5
SMBus Interfaces
Introduction
The PES12T3G2 contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES12T3G2, allowing every register in the device to be read or written by
an external SMBus master. The slave SMBus may also be used to preload the serial EEPROM used for
initialization.The Master SMBus interface provides connection for an optional external serial EEPROM used
for initialization and optional external I/O expanders. Six pins make up each of the two SMBus interfaces.
These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. As shown in
Figure 5.1, the master and slave SMBuses may be used in a unified or split configuration.
Figure 5.1 SMBus Interface Configuration Examples
In the unified configuration, shown in Figure 5.1(a), the master and slave SMBuses are tied together and
the PES12T3G2 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that
the external SMBus master or processor that has access to the PES12T3G2 registers support SMBus arbi-
tration. In some systems, this external SMBus master interface may be implemented using general purpose
I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these
systems, the PES12T3G2 may be configured to operate in a split configuration as shown in Figure 5.1(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-
master arbitration is not required.
Processor
PES12T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES12T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
...
(a) Unified Configuration
(b) Split Configuration
Hot-Plug
I/O
Expander
Hot-Plug
I/O
Expander