IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 28 January 28, 2013
Notes
5 HPS RWL 0x0 Hot Plug Surprise. When set, this bit indicates that a device
present in the slot may be removed from the system without
notice.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
6 HPC RWL 0x0 Hot Plug Capable. This bit is set if the slot corresponding to the
port is capable of supporting hot-plug operations.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
14:7 SPLV RW 0x0 Slot Power Limit Value. In combination with the Slot Power Limit
Scale, this field specifies the upper limit on power supplied by the
slot.
A Set_Slot_Power_Limit message is generated using this field
whenever this register is written or when the link transitions from a
non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
16:15 SPLS RW 0x0 Slot Power Limit Scale. This field specifies the scale used for
the Slot Power Limit Value (SPLV).
0x0 - (x1) 1.0x
0x1 - (xp1) 0.1x
0x2 - (xp01) 0.01x
0x3 - (xp001) 0.001x
A Set_Slot_Power_Limit message is generated using this field
whenever this register is written or when the link transitions from a
non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
17 EIP RWL 0x0 Electromechanical Interlock Present. This bit is set if an elec-
tromechanical interlock is implemented on the chassis for this
slot.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
18 NCCS RO 0x0 No Command Completed Support. Software notification is
always generated when an issued command is completed by the
hot-plug controller. Therefore, this field is hardwired to zero.
31:19 PSLOTNUM RWL 0x0 Physical Slot Number. This field indicates the physical slot num-
ber attached to this port. For devices interconnected on the sys-
tem board, this field should be initialized to zero.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Bit
Field
Field
Name
Type Default
Value
Description