IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 40 January 28, 2013
Notes
AERUEM - AER Uncorrectable Error Mask (0x108)
21 ACSV RW1C 0x0
Sticky
ACS Violation Status. This bit is set when an ACS violation is
detected on the port. The PES12T3G2 does not support ACS
and therefore this bit is hardwired to 0x0.
31:22 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 UDEF RW 0x0
Sticky
Undefined. This bit is no longer used in this version of the speci-
ficiation.
3:1 Reserved RO 0x0 Reserved field.
4 DLPERR RW 0x0
Sticky
Data Link Protocol Error Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an
error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
5 SDOENERR RW 0x0
Sticky
Surprise Down Error Mask. When this bit is set, the correspond-
ing bit in the AERUES register is masked. When a bit is masked
in the AERUES register, the corresponding event is not logged in
the advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
11:6 Reserved RO 0x0 Reserved field.
12 POISONED RW 0x0
Sticky
Poisoned TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
13 FCPERR RW 0x0
Sticky
Flow Control Protocol Error Mask. When this bit is set, the cor-
responding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an
error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
14 COMPTO RO 0x0 Completion Time-out Mask. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hard-
wired to zero.
Bit
Field
Field
Name
Type Default
Value
Description