IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 43 January 28, 2013
Notes
AERCES - AER Correctable Error Status (0x110)
19 ECRC RW 0x0
Sticky
ECRC Severity. If the corresponding event is not masked in the
AERUEM register, then when the event occurs, this bit controls
the severity of the reported error. If this bit is set, the event is
reported as a fatal error. When this bit is cleared, the event is
reported as an uncorrectable error.
20 UR RW 0x0
Sticky
UR Severity. If the corresponding event is not masked in the
AERUEM register, then when the event occurs, this bit controls
the severity of the reported error. If this bit is set, the event is
reported as a fatal error. When this bit is cleared, the event is
reported as an uncorrectable error.
21 ACSV RW 0x0
Sticky
ACS Violation Severity. If the corresponding event is not
masked in the AERUEM register, then when the event occurs,
this bit controls the severity of the reported error. If this bit is set,
the event is reported as a fatal error. When this bit is cleared, the
event is reported as an uncorrectable error.
31:22 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 RCVERR RW1C 0x0
Sticky
Receiver Error Status. This bit is set when the physical layer
detects a receiver error.
5:1 Reserved RO 0x0 Reserved field.
6 BADTLP RW1C 0x0
Sticky
Bad TLP Status. This bit is set when a bad TLP is detected.
7 BADDLLP RW1C 0x0
Sticky
Bad DLLP Status. This bit is set when a bad DLLP is detected.
8 RPLYROVR RW1C 0x0
Sticky
Replay Number Rollover Status. This bit is set when a replay
number rollover has occurred indicating that the data link layer
has abandoned replays and has requested that the link be
retrained.
11:9 Reserved RO 0x0 Reserved field.
12 RPLYTO RW1C 0x0
Sticky
Replay Timer Time-Out Status. This bit is set when the replay
timer in the data link layer times out.
13 ADVISORYNF RW1C 0x0
Sticky
Advisory Non-Fatal Error Status. This bit is set when an advi-
sory non-fatal error is detected as described in Section 6.2.3.2.4
of the PCIe base 1.1 specification.
31:14 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description