IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 133 / 146

IDT Configuration Registers
PES12T3G2 User Manual 8 - 57 January 28, 2013
Notes
GPIOD - General Purpose I/O Data (0x420)
SMBUSSTS - SMBus Status (0x424)
Bit
Field
Field
Name
Type Default
Value
Description
15:0 GPIOD RW HWINIT
Sticky
GPIO Data. Each bit in this field controls the corresponding GPIO
pin. Reading this field returns the current value of each GPIO pin
regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
Writing a value to this field causes the corresponding pins which
are configured as GPIO outputs to change state to the value writ-
ten.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 Reserved RO 0x0 Reserved field.
7:1 SSMBADD
R
RO HWINIT Slave SMBus Address. This field contains the SMBus address
assigned to the slave SMBus interface.
8 Reserved RO 0x0 Reserved field.
15:9 MSMBADD
R
RO HWINIT Master SMBus Address. This field contains the SMBus address
assigned to the master SMBus interface.
23:16 Reserved RO 0x0 Reserved field.
24 EEPROM-
DONE
RO 0x0 Serial EEPROM Initialization Done. When the switch is config-
ured to operate in a mode in which serial EEPROM initialization
occurs during a Fundamental Reset, this bit is set when serial
EEPROM initialization completes or when an error is detected.
25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected NACK is
observed during a master SMBus transaction. The setting of this
bit may indicate the following: that the addressed device does not
exist on the SMBus (i.e., addressing error); data is unavailable or
the device is busy; an invalid command was detected by the slave;
or invalid data was detected by the slave.
26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus interface loses
arbitration for the SMBus, it automatically re-arbitrates for the
SMBus. If the master SMBus interface loses 16 consecutive arbi-
tration attempts, then the transaction is aborted and this bit is set.
27 OTHER-
ERR
RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP condi-
tion is detected by the master SMBus interface.
28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid check-
sum is computed during Serial EEPROM initialization or when a
configuration done command is not found in the serial EEPROM.
29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set if an
attempt is made to initialize via serial EEPROM a register that is
not defined in the corresponding PCI configuration space.
31:30 Reserved RO 0x0 Reserved field.