IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 12 January 28, 2013
Notes
RID - Revision Identification Register (0x008)
CCODE - Class Code Register (0x009)
CLS - Cache Line Size Register (0x00C)
PLTIMER - Primary Latency Timer (0x00D)
14 SSE RW1C 0x0 Signalled System Error. This bit is set when the bridge sends a
ERR_FATAL or ERR_NONFATAL message and the SERR Enable
(SERRE) bit is set in the PCICMD register.
0x0 - (noerror) no error.
0x1 - (error) This bit is set when a fatal or non-fatal error is sig-
nalled.
15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge whenever it
receives a poisoned TLP on the primary side regardless of the
state of the PERRE bit in the PCI Command register.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 RID RWL - Revision ID. This field contains the revision identification number
for the device.
See section Revision ID on page 1-4.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 INTF RO 0x00 Interface. This value indicates that the device is a PCI-PCI bridge
that does not support subtractive decode.
15:8 SUB RO 0x04 Sub Class Code. This value indicates that the device is a PCI-PCI
bridge.
23:16 BASE RO 0x06 Base Class Code. This value indicates that the device is a bridge.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 CLS RW 0x00 Cache Line Size. This field has no effect on the bridge’s function-
ality but may be read and written by software.
This field is implemented for compatibility with legacy software.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 PLTIMER RO 0x00 Primary Latency Timer. Not applicable.
Bit
Field
Field
Name
Type Default
Value
Description