IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Clocking, Reset and Initialization
PES12T3G2 User Manual 2 - 4 January 28, 2013
Notes
remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external
agent may read and write any internal control and status registers and may access the external
serial EEPROM via the EEPROMINTF register.
12. Normal device operation begins.
The PCIe 2.0 specification indicates that a device must respond to Configuration Request transactions
within 100 ms from the end of Conventional Reset (cold, warm, or hot). Additionally, the PCIe specification
indicates that a device must respond to Configuration Requests with a Successful Completion within 1.0
second after Conventional Reset of a device. The reset sequence above guarantees that the PES12T3G2
will be ready to respond successfully to configuration request within the 1.0 second period as long as the
serial EEPROM initialization process completes within 200 ms. During EEPROM initialization, the
PES12T3G2 responds to a Configuration Request with Configuration-Request-Retry-Status Completion.
Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a
Master SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by a configuration request writing a one to the Fundamental Reset (FRST) bit in
the Switch Control (SWCTL) register always results in the PES12T3G2 returning a Successful Completion
to the requester
before the warm reset process begins.
The PES12T3G2 provides a reset output signal for each downstream port implemented as a GPIO alter-
nate function. When a Fundamental Reset occurs, all of the GPIO pins default to GPIO inputs. Therefore,
the downstream port resets are tri-stated. A system designer should use a pull-down on these signals if
they are used as reset outputs.
The operation of a Fundamental Reset with serial EEPROM initialization (i.e., SWMODE[2:0] = 0x1) is
illustrated in Figure 2.1.
Figure 2.1 Fundamental Reset with Serial EEPROM Initialization
The operation of a Fundamental Reset using RSTHALT is illustrated in Figure 2.2.
PExREFCLKP/N
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
Tpvperl
CDR Reset & Lock
Ready for Normal Operation
Ready for Normal Operation
Ready
Idle Serial EEPROM Initialization
Notes:
20 ms max.
Stacks held in Quasi-Reset Mode
Link Training PLL Lock
Tperst-clk
1) Reference Clock (REFCLK) not shown to scale.
2) The PES12T3G2 requires a minimum time for Tperst-clk of 1µs. The PES12T3G2 requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES12T3G2 is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.
1ms max