IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 11 January 28, 2013
Notes
PCISTS - PCI Status Register (0x006)
8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the bridge
are reported to the Root Complex when this bit is set or the bits in
the PCI Express Device Control register are set (see PCIEDCTL -
PCI Express Device Control (0x048)).
In addition, when this bit is set it enables the forwarding of
ERR_NONFATAL and ERR_FATAL error messages from the sec-
ondary to the primary interface. ERR_COR messages are unaf-
fected by this bit and are always forwarded.
0x0 - (disable) Disable non-fatal and fatal error reporting if also
disabled in Device Control register.
0x1 - (enable) Enable non-fatal and fatal error reporting.
9 FB2B RO 0x0 Fast Back-to-Back Enable. Not applicable.
10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to gener-
ate an INTx interrupt message.
When this bit is set, any interrupts generated by this bridge are
negated. This may result in a change in the resolved interrupt state
of the bridge.
This bit has no effect on interrupts forwarded from the secondary to
the primary interface.
15:11 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
2:0 Reserved RO 0x0 Reserved field.
3 INTS RO 0x0 INTx Status. This bit is set when an INTx interrupt is pending from
the device.
INTx emulation interrupts forwarded by switch ports from devices
downstream of the bridge are not reflected in this bit.
For downstream ports, this bit is set if an interrupt has been
“asserted” by the corresponding port’s hot-plug controller.
In the upstream port this field is always zero.
4 CAPL RO 0x1 Capabilities List. This bit is hardwired to one to indicate that the
bridge implements an extended capability list item.
5 C66MHZ RO 0x0 66 MHz Capable. Not applicable.
6 Reserved RO 0x0 Reserved field.
7 FB2B RO 0x0 Fast Back-to-Back (FB2B). Not applicable.
8 MDPED RO 0x0 Master Data Parity Error Detected. Not applicable.
10:9 DEVT RO 0x0 DEVSEL# TIming. Not applicable.
11 STAS RO 0x0 Signalled Target Abort. Not applicable since a target abort is
never signalled.
12 RTAS RO 0x0 Received Target Abort. Not applicable.
13 RMAS RO 0x0 Received Master Abort. Not applicable.
Bit
Field
Field
Name
Type Default
Value
Description