IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 15 January 28, 2013
Notes
SECSTS - Secondary Status Register (0x01E)
MBASE - Memory Base Register (0x020)
MLIMIT - Memory Limit Register (0x022)
Bit
Field
Field
Name
Type Default
Value
Description
7:0 Reserved RO 0x0 Reserved field.
8 MDPED RO 0x0 Master Data Parity Error. Not applicable.
10:9 DVSEL RO 0x0 Not applicable.
11 STAS RO 0x0 Signalled Target Abort Status. Not applicable.
12 RTAS RO 0x0 Received Target Abort Status. Not applicable.
13 RMAS RO 0x0 Received Master Abort Status. Not applicable.
14 RSE RW1C 0x0 Received System Error. This bit is controlled by the SERR enable
bit in the Bridge Control (BCTL) register. If the SERRE bit is
cleared in BCTL, then this bit is never set. Otherwise, this bit is set
if the secondary side of the bridge receives an ERR_FATAL or
ERR_NONFATAL message.
15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge whenever it
receives a poisoned TLP on the secondary side regardless of the
state of the PERRE bit in the PCI Command register
Bit
Field
Field
Name
Type Default
Value
Description
3:0 Reserved RO 0x0 Reserved field.
15:4 MBASE RW 0xFFF Memory Address Base. The MBASE and MLIMIT registers are
used to control the forwarding of non-prefetchable transactions
between the primary and secondary interfaces of the bridge. This
field contains A[31:20] of the lowest address aligned on a 1MB
boundary that is below the primary interface of the bridge.
Bit
Field
Field
Name
Type Default
Value
Description
3:0 Reserved RO 0x0 Reserved field.
15:4 MLIMIT RW 0x0 Memory Address Limit. The MBASE and MLIMIT registers are
used to control the forwarding of non-prefetchable transactions
between the primary and secondary interfaces of the bridge. This
field contains A[31:20] of the highest address, with A[19:0]
assumed to be 0xF_FFFF, that is below the primary interface of
the bridge.