IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT PES12T3G2 Device Overview
PES12T3G2 User Manual 1 - 3 January 28, 2013
Logic Diagram
Figure 1.2 PES12T3G2 Logic Diagram
PE0TP[0]
Reference
Clocks
PEREFCLKP[0]
PEREFCLKN[0]
JTAG_TCK
GPIO[11,7:0]
9
General Purpose
I/O
V
DD
CORE
V
DD
I/O
V
DD
PEA
Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
RSTHALT
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
V
SS
SWMODE[2:0]
3
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PCI Express
Switch
SerDes Input
PE0TN[0]
PE0TP[3]
PE0TN[3]
PCI Express
Switch
SerDes Output
...
Port 0
Port 0
...
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
PCI Express
Switch
SerDes Output
...
Port 2
Port 2
...
PE4RP[0]
PE4RN[0]
PE4RP[3]
PE4RN[3]
PCI Express
Switch
SerDes Input
PE4TP[0]
PE4TN[0]
PE4TP[3]
PE4TN[3]
PCI Express
Switch
SerDes Output
...
Port 4
Port 4
...
PES12T3G2
REFRES0
SerDes
Reference
Resistors
REFRES2
REFRES4
V
DD
PEHA
Reference Clock
Frequency Selection
V
DD
PETA