IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 122 / 146

IDT Configuration Registers
PES12T3G2 User Manual 8 - 46 January 28, 2013
Notes
SNUMUDW - Serial Number Upper Doubleword (0x188)
PCI Express Virtual Channel Capability
PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)
PVCCAP1- Port VC Capability 1 (0x204)
Bit
Field
Field
Name
Type Default
Value
Description
31:0 SNUM RWL 0x0
Sticky
Upper 32-bits of Device Serial Number. This field contains the
upper 32-bits of the IEEE defined 64-bit extended unique identifier
(EUI-64) assigned to the device.
Bit
Field
Field
Name
Type Default
Value
Description
15:0 CAPID RO 0x2 Capability ID. The value of 0x2. indicates a virtual channel capa-
bility structure.
19:16 CAPVER RO 0x1 Capability Version. The value of 0x1. indicates compatibility with
version 1 of the specification.
31:20 NXTPTR RWL 0x0 Next Pointer. The value of 0x0 indicates that there are no
extended capabilities.
Bit
Field
Field
Name
Type Default
Value
Description
2:0 EVCCNT RO 0x0 Extended VC Count. The value 0x0 indicates only implementation
of the default VC.
3 Reserved RO 0x0 Reserved field.
6:4 LPEVCCNT RO 0x0 Low Priority Extended VC Count. The value of 0x0 indicates only
implementation of the default VC.
7 Reserved RO 0x0 Reserved field.
9:8 REFCLK RO 0x0 Reference Clock. WRR is not implemented.
11:10 PATBLSIZ RO Upstream:
0x2
Down-
stream:
0x0
Port Arbitration Table Entry Size. This field indicates the size of
the port arbitration table in the device. For the upstream port, the is
set to 0x2 to indicate a table with 4-bit entries. For downstream
ports, this value is set to 0x0.
0x0 - (bit1) Port arbitration table is 1-bit
0x1 - (bit2) Port arbitration table is 2-bits
0x2 - ((bit4) Port arbitration table is 4-bits
0x3 -(bit8) Port arbitration table is 8-bits
31:12 Reserved RO 0x0 Reserved field.