IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Link Operation
PES12T3G2 User Manual 3 - 2 January 28, 2013
Notes
Figure 3.2 Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH=0x2)
Link Width Negotiation
The PES12T3G2 supports the optional link variable width negotiation feature outlined in the PCIe 2.0
specification. The maximum port link width is discussed in section Port Configuration on page 1-10. The
actual link width is determined dynamically during link training. Ports limited to a maximum link width of x4
are capable of negotiating to a x4, x2, or x1 link width.
The negotiated width of each link after a full link train
1
may be determined from the Negotiated Link
Width (NLW) field in the corresponding port’s PCIe Link Status (PCIELSTS) register. This field indicates the
actual link width at the time the field is read.
The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP)
register contains the maximum link width of the port. This field is of RWL type and may be modified when
the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the maximum link width
of the port to be configured. The new link width takes effect the next time full link training occurs.
When a x4 port negotiates to a width less than x4, the unused SerDes lanes are put in a low power
state. When a port is disabled, all SerDes lanes associated with that port are powered down.
Dynamic Link Width Re-Configuration
Background
The PCI Express 2.0 specification includes support for dynamic upconfiguration of link widths. This
optional capability allows both components of a link to dynamically downconfigure & upconfigure links
based on implementation specific criteria such as power savings, link bandwidth requirements, or link reli-
ability problems.
As an example, a link that initially does a full link train to x4 may be dynamically downconfigured to x1 in
order to save power when there is little traffic on the link. As traffic increases, the link may be dynamically
upconfigured to its initial link width of x4. Also, the link width may be downconfigured if a particular lane is
determined to be unreliable.
With dynamic link width re-configuration, the system designer can choose to connect components with
enough lanes to handle worst case bandwidth requirements, yet not waste power when the link is not fully
utilized. This capability offers an additional mechanism for link power reduction on top of the traditional
ASPM link states (L0s, L1, etc.)
1.
A full link train is a link training in which the LTSSM transitions through the Detect state.
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
lane 1
(a) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 1
lane 0
(b) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
(c) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
(d) x1 Port with lane reversal