IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 26 January 28, 2013
Notes
PCIELSTS - PCI Express Link Status (0x052)
Bit
Field
Field
Name
Type Default
Value
Description
3:0 CLS RO 0x1 Current Link Speed. This field indicates the current link speed of
the port.
1 - (gen1) 2.5 Gbps
2 - (gen2) 5 Gbps
others-reserved
9:4 NLW RO HWINIT Negotiated Link Width. This field indicates the negotiated width of
the link. Defined encodings are:
00 0001b - x1
00 0010b - x2
00 0100b - x4
00 1000b - x8
00 1100b - x12
01 0000b - x16
10 0000b - x32
When the MAXLNKWDTH field in the PCIELCAP register selects a
width not supported by the port, the value of this field corresponds
to the setting of the MAXLNKWDTH field, regardless of the actual
negotiated link width.
When the MAXLNKWDTH field in the PCIELCAP register selects a
width supported by the port, but the link is unable to train, the value
in this field is set to 0x0.
10 TERR RO 0x0 Training Error. In PCIe base 1.0a when set, this bit indicates that
a link training error has occurred.
The value of this field is undefined in the PCIe base 2.0 specifica-
tion.
11 LTRAIN RO 0x0 Link Training. When set, this bit indicates that link training is in
progress.
Specifically, this bit is set when the Physical Layer LTSSM is in the
Configuration or Recovery state, or when a 0x1 was written to the
LRET bit in the PCIELCTL register, but Link training has not yet
begun. Note that in the upstream port, LRET has a delayed effect
of 1 ms.
Hardware clears this bit when the LTSSM exits the Configuration/
Recovery state
12 SCLK RWL HWINIT Slot Clock Configuration. When set, this bit indicates that the
component uses the same physical reference clock that the plat-
form provides. The initial value of this field is the state of the
CCLKUS signal for the upstream port and the CCLKDS signal for
downstream ports. The serial EEPROM may override these default
values.
13 DLLLA RO 0x0 Data Link Layer Link Active. This bit indicates the status for the
data link control and management state machine.
0x0 - (not_active) Data link layer not active state
0x1 - (active) Data link layer active state
This bit must never be set by hardware if the DLLLA bit in the
PCIELCAP register is cleared.