IDT SMBus Interfaces
PES12T3G2 User Manual
5 - 15
January 28, 2013
Notes
The format of the CMD field is shown in Figure 5.7 and described in Table 5.14.
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
4
ADDRL
Address Low. Lower 8-bits of the Serial EEPROM byte to access.
5
ADDRU
Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
6
DATA
Data. Serial EEPROM value read or to be written.
Bit
Field
Name
Type
1
Description
0
OP
RW
Serial EEPROM Operation. This field encodes the serial EEPROM
operation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read
1
USA
RW
Use Specified Address. When this bit is set the serial EEPROM
SMBus address specified in the EEADDR is used instead of that
specified in the ADDR field in the EEPROMINTF register.
When this bit is set the serial EEPROM SMBus address specified in
the EEADDR is used instead of that specified in the MSMBADDR
field in the SMBUSSTS register.
2
Reserved
3
NAERR
RC
No Acknowledge Error. This bit is set if an unexpected NACK is
observed during a master SMBus transaction when accessing the
serial EEPROM. This bit has the same function as the NAERR bit in
the SMBUSSTS register.
The setting of this bit may indicate the following: that the addressed
device does not exist on the SMBus (i.e., addressing error), data is
unavailable or the device is busy, an invalid command was detected
by the slave, invalid data was detected by the slave.
4
LAERR
RC
Lost Arbitration Error. This bit is set if the master SMBus interface
loses 16 consecutive arbitration attempts when accessing the serial
EEPROM. This bit has the same function as the LAERR bit in the
SMBUSSTS register.
5
OTHERERR
RC
Other Error. This bit is set if a misplaced START or STOP condition is
detected by the master SMBus interface when accessing the serial
EEPROM. This bit has the same function as the OTHERERR bit in
the SMBUSSTS register.
7:6
Reserved
0
Reserved. Must be zero.
Table 5.14 Serial EEPROM Read or Write CMD Field Description
Byte
Position
Field
Name
Description
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
OP
USA
0
NAERR
LAERR
OTHERERR
0
Summary of Contents for 89HPES12T3G2
Page 10: ...IDT Table of Contents PES12T3G2 User Manual iv January 28 2013 Notes...
Page 12: ...IDT List of Tables PES12T3G2 User Manual vi January 28 2013 Notes...
Page 14: ...IDT List of Figures PES12T3G2 User Manual viii January 28 2013 Notes...
Page 18: ...IDT Register List PES12T3G2 User Manual xii January 28 2013 Notes...
Page 46: ...IDT Link Operation PES12T3G2 User Manual 3 10 January 28 2013 Notes...
Page 66: ...IDT SMBus Interfaces PES12T3G2 User Manual 5 18 January 28 2013 Notes...
Page 70: ...IDT Power Management PES12T3G2 User Manual 6 4 January 28 2013 Notes...
Page 138: ...IDT Configuration Registers PES12T3G2 User Manual 8 62 January 28 2013 Notes...