IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT PES12T3G2 Device Overview
PES12T3G2 User Manual 1 - 10 January 28, 2013
Notes
Port Configuration
The PES12T3G2 contains a total of three ports labeled 0, 2, and 4. Port 0 is always the upstream port.
Ports 2 and 4 are always downstream ports. All ports can operate at a maximum link width of x4, and all
ports support both 2.5 Gbps and 5.0 Gbps (Gen2). Per the PCIe specification, each switch port corre-
sponds to a virtual PCI-PCI bridge device. In the PES12T3G2, device numbering follows port numbering.
Therefore, Port 0 corresponds to Device 0 on the upstream bus. Port 2 corresponds to Device 2 on the
PES12T3G2’s virtual PCI bus and Port 4 corresponds to Device 4.
Configuration read or write transactions to a non-existent device on the PES12T3G2’s virtual PCI bus
(i.e., Device 0, 1, 3, 5, etc.) are treated by the upstream port (port 0) as an unsupported request (i.e., the
device does not exist). Additionally, SMBus accesses to configuration registers of a non-existent device
have an undefined effect.
Figure 1.3 illustrates a diagram of Whitney with three x4 ports. The figure shows port and device
numbering.
Figure 1.3 PES12T3G2 Port & Device Numbering
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
SerDes Refer-
ence Resistors REFRES0 I/O Analog
REFRES2 I/O
REFRES4 I/O
1.
Internal resistor values under typical operating conditions are 92K
Ω
for pull-up and 90K
Ω
for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 1.9 Pin Characteristics (Part 2 of 2)
PES12T3G2
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 2
PCI to PCI
Bridge
Dev. 4
Dev. 0
Port 0
Virtual PCI Bus
x4
Port 2
x4
Port 4
x4