IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 31 January 28, 2013
Notes
PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064)
PCIEDCTL2 - PCI Express Device Control 2 (0x068)
4 CC RW1C 0x0 Command Completed. This bit is set when the Hot-Plug Control-
ler completes an issued command. If the bit is already set, then it
remains set.
A single write to the PCI Express Slot Control (PCIESCTL) register
is considered to be a single command even if it affects more than
one field in that register. This command completed bit is not set
until processing of all actions associated with all fields in the PCI-
ESCTL register have completed (i.e., all associated SMBus I/O
expander transactions have completed).
5 MRLSS RO 0x0 MRL Sensor State. This field enclosed the current state of the
MRL sensor.
0x0 - (closed) MRL closed
0x1 - (open) MRL open
6 PDS RO 0x1 Presence Detect State. This bit indicates the presence of a card
in the slot corresponding to the port and reflects the state of the
Presence Detect status.
0x0 - (empty) Slot empty
0x1 - (present) Card present
7 EIS RO 0x0 Electromechanical Interlock Status. When an electromechanical
interlock is implemented, this bit indicates the current status of the
interlock.
0x0 - (disengaged) Electromechanical interlock disengaged
0x1 - (engaged) Electromechanical interlock engaged
8 DLLLASC RW1C 0x0 Data Link Layer Link Active State Change. This bit is set when
the state of the data link layer active field in the link status register
changes state.
0x0 - (nochange) No DLLLA state change
0x1 - (changed) DLLLA state change
15:9 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
31:0 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
15:0 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description