IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 23 January 28, 2013
Notes
PCIELCAP - PCI Express Link Capabilities (0x04C)
Bit
Field
Field
Name
Type Default
Value
Description
3:0 MAXLNKSPD RO 0x2 Maximum Link Speed. This field indicates the supported link
speeds of the port.
1 - (gen1) 2.5 Gbps
2 - (gen2) 5 Gbps
others-reserved
The initial value of this field is always 0x2 for the upstream and
downstream ports.
9:4 MAXLNKWDTH RWL HWINIT Maximum Link Width. This field indicates the maximum link
width of the given PCI Express link. This field may be overrid-
den to allow the link width to be forced to a smaller value.
Setting this field to an invalid or reserved value is allowed, and
results in the port operating at its default (i.e., initial) value.
The value written to this field is never modified by hardware.
See section Port Configuration on page 1-10 for more infor-
mation.
0 -
reserved
1 - (x1) x1 link width
2 - (x2) x2 link width
4 - (x4) x4 link width
others-reserved
11:10 ASPMS RO 0x3 Active State Power Management (ASPM) Support. This
field is hardwired to 0x3 to indicate L0s and L1 Support.
14:12 L0SEL RWL HWINIT L0s Exit Latency. This field indicates the L0s exit latency for
the given PCI Express link. The default value of 0x5 corre-
sponds to a L0s exit latency of 1 µ s to 2 µ s.
17:15 L1EL RWL 0x2 L1 Exit Latency. This field indicates the L1 exit latency for the
given PCI Express link. Transitioning from L1 to L0 always
requires 2.3 µ S. Therefore, a value 2 µ s to less than 4 µ s is
reported with a default value of 0x2.
18 CPM RWL 0x0 Clock Power Management. This bit indicates if the compo-
nent tolerates removal of the reference clock via the
“CLKREQ#” machanism.
The PES12T3G2 does not support the removal of reference
clocks.
19 SDERR RWL Upstream:
0x0
Down-
stream:
0x1
Surprise Down Error Reporting. The PES12T3G2 downs-
trem ports support surprise down error reporting.
This field does not apply to an upstream port and should be
hardwired to zero.
20 DLLLA RWL Upstream:
0x0
Down-
stream:
0x1
Data Link Layer Link Active Reporting. The PES12T3G2
downstream ports support the capability of reporting the
DL_Active state of the data link control and management state
machine.
Modification of this bit changes the advertised capability value
but does not modify the device behavior (i.e., status is always
reported regardless of this field value).
This field is not applicable for the upstream port and must be
hardwired to zero.