IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 41 January 28, 2013
Notes
15 CABORT RO 0x0 Completer Abort Mask. The PES12T3G2 never responds to a
non-posted request with a completer abort.
16 UECOMP RW 0x0
Sticky
Unexpected Completion Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an
error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
17 RCVOVR RW 0x0
Sticky
Receiver Overflow Mask. When this bit is set, the corresponding
bit in the AERUES register is masked. When a bit is masked in
the AERUES register, the corresponding event is not logged in
the advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
18 MALFORMED RW 0x0
Sticky
Malformed TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
19 ECRC RW 0x0
Sticky
ECRC Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
20 UR RW 0x0
Sticky
UR Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
21 ACSV RW 0x0
Sticky
ACS Violation Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
31:22 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description