IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Link Operation
PES12T3G2 User Manual 3 - 4 January 28, 2013
Notes
It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the
link at the target link speed or at the highest common speed supported by both components of the link,
whichever is lower. Either link component may request a link speed change due to the following:
– Software commands via the Link Control registers (PCIELCTL and PCIELCTL2)
– Autonomous (i.e., implementation specific) mechanisms
– Link reliability reasons (i.e., speed downgrade).
A component must not initiate a link speed upgrade if it has never recorded support for the higher speed
by its link partner since the last time the component exited the Detect state. Therefore, if a Gen2 capable
component link-trains with a Gen1 only component, the Gen2 capable component will not request a link
speed upgrade.
A component may initiate a link speed change if it has recorded support for the target speed by its link
partner since exiting the Detect state. The link speed change operation via the Recovery state may succeed
or fail, depending on the link partner’s current support for the target speed as well as the link reliability at
that speed. If it fails, the initiating component must wait 200ms before re-trying to upgrade the speed, or
until the link partner advertises support for the higher speed.
The upstream component must initiate a link speed upgrade if it has recorded support for the higher
speed by its link partner since exit from the Detect state, and software sets the Link Retrain bit in the
PCIELCTL register with a target link speed which is not equal to the current link speed. Additionally, the
upstream component (i.e., switch downstream port) is capable of notifying software of link speed changes
via the Link Bandwidth Notification mechanism described in the PCIe 2.0 specification.
Link Speed Negotiation in the PES12T3G2
The PES12T3G2 ports support per lane data rates of 5.0 Gbps and 2.5 Gbps. The highest data rate of
each link is determined dynamically, and depends on the following factors:
– Maximum link data rate supported by both components of the link
– The Target Link Speed set via the Link Control 2 Register (PCIELCTL2)
– The reliability of the link at 5.0 Gbps
By default, the Target Link Speed (TLS) of each port is set to 5.0 Gbps. Therefore, the PES12T3G2
ports advertise support for 2.5 Gbps and 5.0 Gbps during the link training process via training-sets. After a
fundamental reset, each port link trains to the L0 state at 2.5 Gbps. If the Target Link Speed indicates 5.0
Gbps (default value), the PHY LTSSM automatically initiates link speed upgrade to 5.0 Gbps using the link
speed change mechanism described in the PCIe 2.0 specification. This behavior applies to both upstream
and downstream ports.
Note that in this case the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register
of downstream port’s is not set, since the initial link speed upgrade is not caused by a software directed link
retrain or due to link reliability issues. The same behavior applies after full link retrain (i.e., when the LTSSM
transitions through the ‘Detect’ state).
The current link speed of each port is reported via the Current Link Speed (CLS) field of the port’s Link
Status Register (PCIELSTS). Assuming the target link speed is set to 5.0 Gbps, the PES12T3G2 port initi-
ates a link speed upgrade in the following cases:
– Link speed upgrade after initial link train to L0 at 2.5 Gbps, when the link partner advertised
support for the higher speed.
– Link speed upgrade after full link retrain (i.e., via the Detect state) to L0 at 2.5 Gbps, when the link
partner advertised support for the higher speed.
– Software sets the Link Retrain (LRET) bit in the PCIELCTL register, and the PES12T3G2 port has
recorded support for the higher speed by its link partner since exit from the Detect state.