IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 36 January 28, 2013
Notes
Message Signaled Interrupt Capability Structure
MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)
8 PMEE RW 0x0
Sticky
PME Enable. When this bit is set, PME message generation is
enabled for the port.
If a hot plug wake-up event is desired when exiting the D3
cold
state, then this bit should be set during serial EEPROM initializa-
tion.
A hot reset does not result in modification of this field.
12:9 DSEL RO 0x0 Data Select. The optional data register is not implemented.
14:13 DSCALE RO 0x0 Data Scale. The optional data register is not implemented.
15 PMES RW1C 0x0
Sticky
PME Status. This bit is set if a PME is generated by the port
even if the PMEE bit is cleared. This bit is not set when the
bridge is propagating a PME message but the port is not itself
generating a PME.
Since the upstream port never generates a PME, this bit will
never be set in that port.
21:16 Reserved RO 0x0 Reserved field.
22 B2B3 RO 0x0 B2/B3 Support. Does not apply to PCI Express.
23 BPCCE RO 0x0 Bus Power/Clock Control Enable. Does not apply to PCI
Express.
31:24 DATA RO 0x0 Data. This optional field is not implemented.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 CAPID RO 0x5 Capability ID. The value of 0x5 identifies this capability as a MSI
capability structure.
15:8 NXTPTR RWL 0x0 Next Pointer. This field contains a pointer to the next capability
structure. This field is set to 0x0 indicating that it is the last capabil-
ity.
16 EN RW 0x0 Enable. This bit enables MSI.
0x0 - (disable) disabled
0x1 - (enable) enabled
19:17 MMC RO 0x0 Multiple Message Capable. This field contains the number of
requested messages.
22:20 MME RW 0x0 Multiple Message Enable. Hardwired to one message.
23 A64 RO 0x1 64-bit Address Capable. The bridge is capable of generating
messages using a 64-bit address.
31:24 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description