Hill-Rom Advanta P1600, Service Manual

Page: 168 / 429

Theory of Operation
Chapter 3: Theory of Operation
Page 3 - 30 Advanta™ Bed Service Manual (man168ra)
Output Protection
The output pin 6 of U7 cannot exceed the supply voltage by more than 0.5
volts, nor can it drop below the ground potential by 0.5 volts. Therefore, any
voltage build-up across voltage suppressor D15 must be clamped within 0.5
volts of the rails. To compensate for the approximately 0.7 volt turn-on voltage
of D17, zener diode D16 and resistor R50 create a lower rail voltage of
approximately 4.7 volts as a reference for clamping diode D17. Likewise, D19
and R49 create a (Vcc - 4.7) volt reference for clamping diode D18. R51 limits
current during transient events, yet provides low line impedance during normal
operation.
Capacitor C21 absorbs transient currents while R47 limits any current caused
by ESD.
EEPROM
Upon reset, the control processor reads the offset compensation constants from
EEPROM. To do so, a logic level 0 (low) is applied to P131 pin 15
(EEPROM_CS). This results in a logic level 1 (high) at the chip select U3 pin 1
enabling the EEPROM. A 0 is then applied to P131 pin 4 (DATA_IN) as a start
bit of 1 at U3 pin 3. A 0-1-0 clock pulse is then applied to P131 pin 14 (CLK).
The low-to-high transition of the inverted pulse at U3 pin 2 causes the start bit
to be clocked into the EEPROM as the first bit of the read instruction. The
remainder of the read instruction is sent by clocking in seven more bits,
10XXX, where 10 is the opcode for READ, and XXXXX is the complement of
the address of the word being read. The next 16 clocks at P131 pin 14 clock the
16 bit word out of U3 pin 4 on the U3 pin 2 rising edge. The most significant
bit (MSB) is clocked out first, the least significant bit (LSB) last.
Resistor R24 acts as a current limiter which protects U3 should a latch-up
condition occur. C11 provides decoupling.
Digital-to-Analog Converter
NAND gate U7 pin 1 acts as a D/A chip select pin. A logic level 0 at P131 pin
3 (A/D_D/A_CS) enables the CLK signal to the shift register U8. The
complement of the MSB of the incoming byte is applied to P131 pin 4
(DATA_IN). A 1-0-1 clock pulse is then applied to P131 pin 14 (CLK). The
low-to-high transition of the pulse at U2 pin 8 causes the MSB to be clocked
into the shift register. The remainder of the byte is sent by clocking in the
complement of the seven remaining bits. After the eight clocks, the MSB is
seen at U2 pin 13, and the LSB is seen at pin 3.