Fuji Electric Faldic-a Series, User Manual, Page: 90 / 251

MHT258a (Engl.) 5-7
5.2.3 Ready [RDY]
This signal turns on when the motor can be rotated.
Listed below are five conditions for turning on this signal.
1) Run command [RUN] (1) signal on
2) Forced stop [EMG] (10) signal on
3) Alarm detection (16) signal off
4) External fault input (34) signal on
5) Free-run [BX] (54) signal off
When the host controller receives the on/off status of [RDY] signal, it recognizes that the motor can be rotated.
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Interface
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Parameter setting
To allocate the ready [RDY] signal to the control output terminal, set (1) to the system para.
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Related items
The amplifier can also output “CPU ready” [CPURDY] (28) signal, which is turned on when the power is being supplied to amplifier and the
internal CPU is processing normally.
For alarm detection (16) signal, see 5.2.4.
For external fault input (34) signal, see 5.5.5.
For free-run [BX] (54) signal, see 5.7.7.
Ready [RDY] (1)
ON : The motor can be rotated.
OFF : Motor cannot be rotated.
APS30
APS30 APS30
APS30
PWR PWR PWR PWR
ALM ALM ALM ALM
ＳＸ ＳＸ ＳＸ ＳＸ
SCPU32
SCPU32 SCPU32
SCPU32
LOADER LOADER LOADER LOADER
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM ALM ALM ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1 O N L C H 1 O N L C H 1 O N L C H 1
E R R C H 2 E R R C H 2 E R R C H 2 E R R C H 2
E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T
2 0
2 0 2 0
2 0
1
11
1
B / A B / A B / A B / A
HP2 HP2 HP2 HP2
O N L O N L O N L O N L
E R R
E R R E R R
E R R
PE1 PE1 PE1 PE1
PH PH PH PH
PL
PL PL
PL
DA
DA DA
DA
C H C H C H C H
N o .
N o . N o .
N o .
SCPU32
SCPU32 SCPU32
SCPU32
LOADER LOADER LOADER LOADER
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM ALM ALM ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
K80791234
K80791234 K80791234
K80791234
L1
L1 L1
L1
L2 L2 L2 L2
L3 L3 L3 L3
DB
DB DB
DB
P1
P1 P1
P1
N N N N
P+
P+ P+
P+
U U U U
V V V V
W
W W
W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT
SHIFT SHIFT
SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE
MODE MODE
MODE
ESC ESC ESC ESC
K80791234
K80791234 K80791234
K80791234
L1
L1 L1
L1
L2 L2 L2 L2
L3 L3 L3 L3
DB
DB DB
DB
P1
P1 P1
P1
N N N N
P+
P+ P+
P+
U U U U
V V V V
W
W W
W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT
SHIFT SHIFT
SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE
MODE MODE
MODE
ESC ESC ESC ESC
Run command [RUN]
Ready [RDY]
+24V