Fuji Electric Faldic-a Series, User Manual

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MHT258a (Engl.) 5-45
・ Origin LS (limit switch) detection (40)
Because the origin LS signal requires quick response, this should be directly input to the amplifier in general. When the host controller
needs the origin signal, the origin LS detection signal can be output.
While the origin LS [LS] signal is on, the origin LS detection signal (40) is on.
・ LS-Z pulse
The encoder pulse count from the time when the origin LS signal goes to OFF level until Z-phase signal is detected can be monitored.
[
]
If this count is small, Z-phase signal of one rotation later may have been detected, depending on the origin LS response. Move the
mechanical position of the origin LS.
Origin LS detection
Origin LS
APS30
APS30 APS30
APS30
PWR PWR PWR PWR
ALM ALM ALM ALM
ＳＸ ＳＸ ＳＸ ＳＸ
SCPU32 SCPU32 SCPU32 SCPU32
LOADER
LOADER LOADER
LOADER
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU
CPU CPU
CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR ERR
RUN
RUN RUN
RUN
ALM
ALM ALM ALM
BAT
BAT BAT BAT
ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7
ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415
ONL CH1 ONL CH1 ONL CH1 ONL CH1
ERR CH2 ERR CH2 ERR CH2 ERR CH2
EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT
20
20 20
20
1
11
1
B/A
B/A B/A
B/A
HP2 HP2 HP2 HP2
ONL ONL ONL ONL
ERR ERR ERR ERR
PE1 PE1 PE1 PE1
PH PH PH PH
PL PL PL PL
DA DA DA DA
CH
CH CH
CH
No.
No. No.
No.
SCPU32 SCPU32 SCPU32 SCPU32
LOADER
LOADER LOADER
LOADER
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU
CPU CPU
CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR ERR
RUN
RUN RUN
RUN
ALM
ALM ALM ALM
BAT
BAT BAT BAT
ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7
ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3 L3 L3 L3
DB
DB DB
DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE
CHARGE CHARGE
CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS
RYS20 1 S3-VVS RYS20 1 S3-VVS
RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3 L3 L3 L3
DB
DB DB
DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE
CHARGE CHARGE
CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS
RYS20 1 S3-VVS RYS20 1 S3-VVS
RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC