Fuji Electric Faldic-a Series, User Manual, Page: 106 / 251

MHT258a (Engl.) 5-23
5.5 Signal for safety
This section explains the functions and input/output signals for safety operation contained in amplifier.
Control input signal : Forced stop [EMG](10)
Edit permit command (55)
+ direction overtravel [+OT] ( 7), - direction overtravel [-OT] ( 8)
Torque limit [TLMT](30)
External fault input (34)
Control output signal : Forced stop detection (41)
Edit permit on (29)
OT detection (20)
+OT detection (38), -OT detection (39)
Torque limit detection (26)
Overload early warning (27)
5.5.1 Forced stop [EMG], Forced stop detection
Stops the motor forcibly using the signal to control input terminal.
While the forced stop (10) signal is off, the motor forced stop is kept.
This input signal is always effective in any control condition, and has the highest priority. (all other commands are ignored.)
Normally, connect this terminal to a push-lock type (NC contact) pushbutton switch (FUJI
’ s COMMAND SWITCH recommended).
■
Interface
Forced stop [EMG] (10)
ON : Motor can rotate.
OFF : Stops the motor forcibly
Forced stop detection (41)
ON : Forced stop is off.
OFF : Forced stop is on.
APS30 APS30 APS30 APS30
PWR
PWR PWR
PWR
ALM ALM ALM ALM
ＳＸ ＳＸ ＳＸ ＳＸ
SCPU32 SCPU32 SCPU32 SCPU32
LOADER LOADER LOADER LOADER
RUN
RUN RUN
RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU
CPU CPU
CPU
No. No. No. No.
ONL
ONL ONL
ONL
ERR ERR ERR ERR
RUN RUN RUN RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1
O N L C H 1 O N L C H 1
O N L C H 1
E R R C H 2 E R R C H 2 E R R C H 2 E R R C H 2
E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T
2 0 2 0 2 0 2 0
1 11 1
B / A
B / A B / A
B / A
HP2 HP2 HP2 HP2
O N L
O N L O N L
O N L
E R R E R R E R R E R R
PE1 PE1 PE1 PE1
PH
PH PH
PH
PL PL PL PL
DA DA DA DA
C H C H C H C H
N o .
N o . N o . N o .
SCPU32 SCPU32 SCPU32 SCPU32
LOADER LOADER LOADER LOADER
RUN
RUN RUN
RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU
CPU CPU
CPU
No. No. No. No.
ONL
ONL ONL
ONL
ERR ERR ERR ERR
RUN RUN RUN RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3
L3 L3
L3
DB DB DB DB
P1 P1 P1 P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT
SHIFT SHIFT
SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE
MODE MODE
MODE
ESC ESC ESC ESC
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3
L3 L3
L3
DB DB DB DB
P1 P1 P1 P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT
SHIFT SHIFT
SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE
MODE MODE
MODE
ESC ESC ESC ESC
P24
M24
2.2k
+24V
+24V