Fuji Electric Faldic-a Series, User Manual

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MHT258a (Engl.) 5-15
5.4 Position control
This section explains the signals related to position control using pulse train input.
Control input signal: Position control (37)
Pulse train ratio 1 (27)
Pulse train ratio 2 (28)
Deviation clear (50)
Position preset (16)
Current position output (56)
Control output signal: Deviation zero (23)
Deviation excessive
5.4.1 Position control
When this signal turns on, the amplifier enters the position control mode.
While the position control (37) signal turns on, the amplifier is in position control. Positioning using pulse train input, origin return and interrupt
positioning is available.
(1) Pulse train input
While pulse train ratio 1 (27) or 2 (28) is on, pulse train input is valid. (Position control (37) on is necessary.)
(2) Origin return
See 5.7 for origin return operation.
(3) Interrupt positioning
See 5.7 for interrupt positioning.
■
Interface
Position control
ON : In position control mode
OFF : In speed control mode
Pulse train ratio 1, 2
ON : Pulse train input is valid
OFF: Pulse train input is ignored
Pulse train input
Max. input frequency 400kHz
Pulse train
Position control (37)
Pulse train ratio 1 (27)
APS30
APS30 APS30
APS30
PWR PWR PWR PWR
ALM
ALM ALM
ALM
ＳＸ
ＳＸ ＳＸ
ＳＸ
SCPU32 SCPU32 SCPU32 SCPU32
LOADER LOADER LOADER LOADER
RUN RUN RUN RUN
TERM
TERM TERM
TERM
SLV
SLV SLV
SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN RUN RUN RUN
ALM
ALM ALM
ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1 O N L C H 1 O N L C H 1 O N L C H 1
E R R C H 2
E R R C H 2 E R R C H 2
E R R C H 2
E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T
2 0
2 0 2 0
2 0
1
11
1
B / A B / A B / A B / A
HP2 HP2 HP2 HP2
O N L O N L O N L O N L
E R R
E R R E R R
E R R
PE1 PE1 PE1 PE1
PH PH PH PH
PL
PL PL
PL
DA DA DA DA
C H
C H C H
C H
N o .
N o . N o . N o .
SCPU32 SCPU32 SCPU32 SCPU32
LOADER LOADER LOADER LOADER
RUN RUN RUN RUN
TERM
TERM TERM
TERM
SLV
SLV SLV
SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN RUN RUN RUN
ALM
ALM ALM
ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3
L3 L3
L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V VV V
W
WW
W
CHARGE CHARGE CHARGE CHARGE
FALDIC
FALDIC FALDIC
FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT
ENT ENT
ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC
ESC ESC
ESC
K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L2
L2 L2
L2
L3
L3 L3
L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V VV V
W
WW
W
CHARGE CHARGE CHARGE CHARGE
FALDIC
FALDIC FALDIC
FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT
ENT ENT
ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC
ESC ESC
ESC
P24
M24
2.2k
+24V
470
×
3
P5
M5
AM26LS32