Digital Equipment DEC 3000 600 AXP, Service Information

Page: 147 / 461

Overview
Memory
Subsystem The memory subsystem includes the following:
• Four memory motherboards (MMB) that mount on the
system module. To have an operational memory subsystem,
all four MMBs must be present.
• The memory arrays are spread among the four MMBs. Each
bank of memory consists of eight memory modules, two on
each MMB.
The memory subsystem supports up to 1 gigabyte (GB) of
memory.
The DEC 3000 Model 800/800S AXP system contains a high-
performance memory subsystem that uses ECC logic. Memory
can be configured with up to 256 MB using 1M
2
4 DRAMs or up
to 1 GB using 4M
2
4 DRAMs.
CPU/Cache The DEC 3000 Model 800/800S AXP system contains a single
chip processor and floating point running at 5.0 ns. The
processor is a superscalar, superimplementation of the Alpha
AXP architecture.
The DEC 3000 Model 800/800S AXP system contains the
following direct-mapped caches:
• Icache (instruction cache)
• Dcache (data cache)
The system uses a second-level cache to help minimize the
performance penalty of misses and write-throughs to the primary
cache. This second-level cache is a 2 MB, direct-mapped,
write-back cache with a block size of 32 bytes.
The cache is implemented on the system module using 128 KB
2
8 static RAMs. The read bandwidth between the processor and
the second level cache is approximately 640 MB and the write
bandwidth is 420 MB.
6–4