Power-Up 2-13
After jumping to the primary CPU’s S-cache, the code then intentionally I-caches
itself and is completely register based (no D-stream for stack or data storage is used).
The only D-stream accesses are writes/reads during testing.
Each FEPROM has sixteen 64-Kbyte sectors. The first sector contains B-cache tests,
memory tests, and a fail-safe loader. The second sector contains support for 1200
system memory and PALcode. The third sector contains a copy of the first sector.
The remaining thirteen sectors contain the SRM console and decompression code.
NOTE: Memory tests are run during power-up and reset (see Table 2-4). They are
also affected by the state of the memory_test environment variable, which can have
the following values:
FULL
Test all memory
PARTIAL
Test up to the first 256 Mbytes
NONE
Test 32 Mbytes
Table 2-3 XSROM Tests
Test
Test Name
Logic Tested
11
B-cache Tag Data Line test
Access to B-cache tags, shorts between tag data
and its status and parity bits
12
B-cache Tag March test
B-cache tag store RAMs, B-cache STAT store
RAMs
13
B-cache Data Line test
B-cache data lines to B-cache data RAMs,
B-cache read/write logic
14
B-cache Data March test
B-cache data RAMs, CPU chip B-cache
control, CPU chip B-cache address decode,
INDEX_H<2x:6> (address bus)
15
B-cache ECC Data Line test
CPU chip ECC generation and checking logic,
ECC lines from CPU chip to B-cache, B-cache
ECC RAMs
16
B-cache Data ECC March test
Portion of B-cache data RAMs used for ECC
17
CPU chip ECC Single/Double bit
Error test
CPU chip ECC single-bit error detection and
correction, ECC double-bit error detection,
ECC error reporting
18
B-cache Tag Store Parity Error
test
B-cache tag array, CPU parity detection,
EI_ADDR and EI_STAT register operation
19
B-cache STAT Store Parity Error
test
B-cache STAT array, CPU chip B-cache STAT
parity generation/detection
