5-14
Service Manual PRELIMINARY
5.1.4
PCI Error Status Register 1 (PCI_ERR1 - Offset = 1040)
PCI_ERR1 is used by the system bus to PCI bus bridge to log bus address
<31:0> pertaining to an error condition logged in CAP_ERR. This register
always captures PCI address <31:0>, even for a PCI DAC cycle. When the
PCI_ERR_VALID bit in CAP_ERR is clear, the contents are undefined.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
00
Failing Address ADDR<31:0>
Table 5-6 PCI Error Status Register 1
Name
Bits
Type
Initial
State
Description
ADDR<31:0>
<31:0>
RO
0
Contains address bits
<31:0> of the transaction
on the PCI bus when an
error is detected.
