2-6
For the console to run, the path from the CPU to the XSROM must be functional.
The XSROM resides in FEPROM0 on the XBUS, off the EISA bus, off PCI 0, off
IOD 0. See Figure 2-4. This path is minimally tested by SROM. .
Figure 2-4 Console Code Critical Path (1200 Block Diagram)
XBUS
Xceivers
I C Bus
2
Interface
Mouse/
Keyboard
Combo I/O:
serial ports
parallel port
floppy cntrl
Real-Time
Clock
BDATA
Xceivers
XBUS
EISA
Bus
PKW0502A-97
PCI Bus 1
System Bus
Memory
Pair
CPU
PCI Slot
PCI Slot
PCI Bus 0
System to
PCI Bus
Bridge 0
IOD0
System to
PCI Bus
Bridge 1
IOD1
PCI Slot
PCI Slot
EISA
Bridge
PCI Slot
PCI Slot
EISA Slot
128-Bit Data Bus + 16 ECC and 40-Bit Command/Address Bus
64 Bits
64 Bits
System
Motherboard
Flash
ROM
2MB
NVRAM
8Kx8
Note: When the EISA slot on
PCI Bus 0 is used, the last
PCI slot on PCI Bus 1 is not
available.
