Power-Up 2-21
²
At power-up or reset, the SROM code on each CPU module is loaded into
that module’s I-cache and tests the module. If all tests pass, the processor’s
LED lights. If any test fails, the LED remains off and power-up testing
terminates on that CPU.
The first determination of the primary processor is made, and the primary
processor executes a loopback test to each PCI bridge. If this test passes, the
bridge LED lights. If it fails, the LED remains off and power-up continues.
The EISA system controller, PCI-to-EISA bridge, COM1 port, and control
panel port are all initialized thereafter.
Each CPU prints an SROM banner to the device attached to the COM1 port
and to the control panel display. (The banner prints to the COM1 port if the
console environment variable is set to serial. If it is set to graphics, nothing
prints to the console terminal, only to the control panel display, until
·)
.
³
Each processor's S-cache is initialized, and the XSROM code in the FEPROM
on the PCI 0 is unloaded into them. (If the unload is not successful, a copy is
unloaded from a different FEPROM sector. If the second try fails, the CPU
hangs.)
Each processor jumps to the XSROM code and sends an XSROM banner to
the COM1 port and to the control panel display.
´
The three S-cache banks on each processor are enabled, and then the
B-cache is tested. If a failure occurs, a message is sent to the COM1 port and
to the control panel display.
Each CPU sends a B-cache completion message to COM1.
µ
The primary CPU is again determined, and memory is sized using code in
sector 1 of FEPROM 0.
The information on memory pairs is sent to COM1. If an illegal memory
configuration is detected, a warning message is sent to COM1 and the control
panel display.
¶
Memory is initialized and tested, and the test trace is sent to COM1 and the
control panel display. Each CPU participates in the memory testing. The
numbers for tests 20 and 21 might appear interspersed, as in Example 2–1.
This is normal behavior. Test 24 can take several minutes if the memory is
very large. The message “P0 TEST 24 MEM**” is displayed on the control
panel display; the second asterisk rotates to indicate that testing is continuing.
If a failure occurs, a message is sent to the COM1 port and to the control
panel display.
Each CPU sends a test completion message to COM1.
Continued on next page
