5-8
Service Manual PRELIMINARY
5.1.2
MC Error Information Register 0
(MC_ERR0 - Offset = 800)
The low-order MC bus (system bus) address bits are latched into this register
when the system bus to PCI bus bridge detects an error event. If the event is a
hard error, the register bits are locked. A write to clear symptom bits in the
CAP Error Register unlocks this register. When the valid bit
(MC_ERR_VALID) in the CAP Error Register is clear, the contents are
undefined.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
00
Failing Address ADDR<31:04>
0
Table 5-3 MC Error Information Register 0
Name
Bits
Type
Initial
State
Description
ADDR<31:4>
<31:4>
RO
0
Contains the address of the
transaction on the system
bus when an error is
detected.
Reserved
<3:0>
RO
0
