4-32
Service Manual PRELIMINARY
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will
Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts
Enabled.
ICACHE BIST (Self Test) Was
Successful.
TEST_STATUS_H Pin Asserted
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg x0000000140008000
Memory Mgmt Flt Sts Reg x0000000000005F10
If Err, Reference Resulted in DTB
Miss
Fault Inst RA Field:
x000000000000001C
Fault Inst Opcode:
x000000000000000B
Scache Address Reg xFFFFFF0000018FEF
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF8061CD0FFF
Last Bcache Access Resulted in a
Miss.
Value of Parity Bit for Tag Control
Status
Bits Dirty, Shared & Valid is
Clear.
Value of Tag Control Dirty Bit is
Clear.
Value of Tag Control Shared Bit is
Clear.
Value of Tag Control Valid Bit is
Set.
Value of Parity Bit Covering Tag
Store
Address Bits is Clear.
Tag Address<38:20> Is:
x000000000000061C
Ext Interface Address Reg xFFFFFF006000050F
Fill Syndrome Reg x0000000000000C0C
Ext Interface Status Reg xFFFFFFF005FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF00002006FF
** IOD SUBPACKET -> ** IOD 0 Register Subpacket
WHOAMI x000002FA Module Revision 0.
VCTY ASIC Rev = 1
Bcache Size = 4MB
CPU = 0
This Bus Bridge Phy Addr x000000F9E0000000
IOD# 0
Dev Type & Rev Register x0600A332 CAP Chip Revision: x00000002
Host to PCI Revision: x00000003
I/O Backplane Revision: x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host Bus to PCI Bridg
MC-PCI Command Register x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions: Enabled
Bridge REQUESTS 64 Bit Data Transactions
