System Overview 1-21
The system bus to PCI bus bridge module converts system bus commands and data
addressed to I/O space to PCI commands and data; and converts PCI bus commands
and data addressed to system memory or CPUs to system bus commands and data.
The bridge has two major components:
•
Command/address processor (CAP) chip
•
Two data path chips (MDPA and MDPB)
There are two sets of these three chips, one set for each PCI.
The interface on the system bus side of the bridge responds to system bus
commands addressed to the upper 64 Gbytes of I/O space. I/O space is addressed
whenever bit <39> on the system bus address lines is set. The space so defined is
512 Gbytes in size. The first 448 Gbytes are reserved and the last 64 Gbytes, when
bits <38:36> are set, are mapped to the PCI I/O buses.
The interface on the PCI side of the bridge responds to commands addressed to
CPUs and memory on the system bus. On the PCI side, the bridge provides the
interface to the PCIs. Each PCI bus is addressed separately. The bridge does not
respond to devices communicating with each other on the same PCI bus. However,
should a device on one PCI address a device on the other PCI bus, commands,
addresses, and data run through the bridge out onto the system bus and back through
the bridge to the other PCI bus.
In addition to its bridge function, the system bus to PCI bus bridge module monitors
every transaction on the system bus for errors. It monitors the data lines for ECC
errors and the command/address lines for parity errors.
