Error Logs 4-15
4.3.2
MCHK 670 CPU and IOD-Detected Failure
The error log in Example 4–1 shows the following:
²
CPU1 logged the error in a system with two CPUs.
³
The External Interface Status Register logged an uncorrectable ECC error
during a D-ref fill. (When a CPU chip does not find data it needs to perform a
task in any of its caches, it requests data from off the chip to fill its D-cache.
It performs a “D-ref fill.”) Bit <30> is set, indicating that the source of the
error is memory or the system. Bits <32> and <35> are set, indicating an
uncorrectable ECC error and a second external interface hard error,
respectively.
´
Both IOD CAP Error Registers logged an error.
µ
The command at the time of the error was a read.
¶
The bus master at the time of the error was CPU3.
·
The Dirty bit, bit <20> in the MC_ERR1 Register is clear, indicating the data
is clean and comes from memory.
The error was detected by a CPU, and the data was on the system bus and is clean.
Therefore, a memory module provided the wrong data. (If the Dirty bit had been set,
the data would have come from the cache of another CPU.) To determine which
memory, see Section 4.4
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10
for information on node IDs.
