2-8
2.3
SROM Power-Up Test Flow
The SROM tests the CPU chip and the path to the XSROM.
Figure 2-5 SROM Power-Up Test Flow
For each CPU
Initialize CPU chip
Turn off CPU LED
Light CPU LED
Dupilcate Tag or
Fill errors
Loopback on
each IOD
HANG
HANG
HANG
All 3 S-cache
banks pass
HANG
D-cache
errors
Determine Primary
Size IOD
Initialize
PCI-EISA bridge
chip
Initialize Combo Chip
on XBUS for access
to COM port 1
Read TOY
NVRAM
Initialize OCP port
on XBUS for access
to OCP display
Initialize all S-cache
banks
Jump to XSROM
overlay in S-cache
Load first 8K of
XSROM into
S-cache
Check integrity of
XSROM
Fail
Fail
twice
Pass
Pass
Yes
Yes
No
Yes
No
No
PKW0432-96
Print to console
device and OCP
Light IOD LEDs
