Error Registers 5-7
Table 5-2 Loading and Locking Rules for External
Interface Registers
Correct
-able
Error
Uncorrect-
able Error
Second
Hard
Error
Load
Register
Lock
Register
Action When
EI_STAT Is Read
0
0
Not
possible
No
No
Clears and unlocks
all registers
1
0
Not
possible
Yes
No
Clears and unlocks
all registers
0
1
0
Yes
Yes
Clears and unlocks
all registers
1
1
1
0
Yes
Yes
Clear bit (c) does
not unlock.
Transition to
“0,1,0” state.
0
1
1
No
Already
locked
Clears and unlocks
all registers
1
1
1
1
No
Already
locked
Clear bit (c) does
not unlock.
Transition to
“0,1,1” state.
1
These are special cases. It is possible that when EI_ADDR is read, only the correctable error bit is set and
the registers are not locked. By the time EI_STAT is read, an uncorrectable error is detected and the
registers are loaded again and locked. The value of EI_ADDR read earlier is no longer valid. Therefore, for
the “1,1,x” case, when EI_STAT is read correctable, the error bit is cleared and the registers are not
unlocked or cleared. Software must reexecute the IPR read sequence. On the second read operation, error
bits are in “0,1,x” state, all the related IPRs are unlocked, and EI_STAT is cleared.
