4-22
Service Manual PRELIMINARY
PAL Shadow Registers Enabled.
Correctable Error Interrupts
Enabled.
ICACHE BIST (Self Test) Was
Successful.
TEST_STATUS_H Pin Asserted
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg x0000000000044000
Memory Mgmt Flt Sts Reg x0000000000005D10
If Err, Reference Resulted in DTB
Miss
Fault Inst RA Field:
x0000000000000014
Fault Inst Opcode:
x000000000000000B
Scache Address Reg xFFFFFF00000254BF
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF8007EE2FFF
Last Bcache Access Resulted in a
Miss.
Value of Parity Bit for Tag Control
Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is
Clear.
Value of Tag Control Shared Bit is
Clear.
Value of Tag Control Valid Bit is
Clear.
Value of Parity Bit Covering Tag
Store ddress Bits is Set.
Tag Address<38:20> Is:
x000000000000007E
Ext Interface Address Reg xFFFFFF0007FBF08F
Fill Syndrome Reg x000000000000D189
Ext Interface Status Reg xFFFFFFF944FFFFFF
Error Source is Memory or System
UNCORRECTABLE ECC ERROR
Error Occurred During D-ref Fill
Error
LD LOCK xFFFFFF0007FBF00F
** IOD SUBPACKET -> ** IOD 0 Register Subpacket
WHOAMI x000000BA Module Revision 0.
VCTY ASIC Rev = 0
Bcache Size = 2MB
MID 2.
GID 7.
Base Address of Bridge x000000F9E0000000
Dev Type & Rev Register x06008021 CAP Chip Revision
x00000001
Host to PCI Revision x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register x06480FF1 Module SelfTest Passed LED on
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions: Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check: Enabled
MC Bus CMD/Addr Parity Check: Enabled
MC Bus NXM Check: Enabled
