Viavi T-BERD MTS 5800, Руководство по началу работы

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Appendix A Specifications
MSAM specifications
T-BERD/MTS/SC Getting Started Guide
Page 186 22046537, Rev. 016 March 2018
DTE emulation
Table 61 lists specifications for EIA-530/EIA-530A balanced testing in DTE emulation
mode.
DCE emulation
Table 62 lists specifications for balanced EIA-530/EIA-530A testing in DCE emulation
mode.
Table 61 EIA-530/EIA-530A balanced DTE emulation specifications
Specification Description
User controllable leads – RTS
– DTR
– LL
– RL
Sync Timing Mode
Rx Timing Sources
– Interface (from the RT circuit)
– Interface Recovered
Sync Timing Mode
Tx Timing Sources
– Interface (from the RT circuit)
– Interface (from the ST circuit)
– Interface Recovered
– Internal Synthesizer
– External Clock
Table 62 EIA-530/EIA-530A balanced DCE emulation specifications
Specification Description
User controllable leads – RLSD
– DSR
– CTS
– TM
– RI (for EIA-530A only)
Sync Timing Mode
Rx Timing Sources
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered
Sync Timing Mode
Tx Timing Sources
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered