Debug support (DBG)
RM0365
1057/1080
DocID025202 Rev 7
Bit 22
DBG_I2C2_SMBUS_TIMEOUT:
SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21
DBG_I2C1_SMBUS_TIMEOUT:
SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12
DBG_IWDG_STOP:
Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11
DBG_WWDG_STOP:
Debug window watchdog stopped when core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10
DBG_RTC_STOP
: Debug RTC stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
Bits 9:5 Reserved, must be kept at reset value.
Bit 4
DBG_TIM6_STOP
: TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped and the output is disabled when the core is halted
Bit 3 Reserved, must be kept at reset value.
Bit 2
DBG_TIM4_STOP
: TIM4 counter stopped when core is halted (Available on STM32F302xB/C
devices only)
0: The counter clock of TIM4 is fed even if the core is halted
1: The counter clock of TIM4 is stopped and the output is disabled when the core is halted
Bit 1
DBG_TIM3_STOP
: TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped and the output is disabled when the core is halted
Bit 0
DBG_TIM2_STOP:
TIM2 counter stopped when core is halted
0: The counter clock of TIM2 is fed even if the core is halted
1: The counter clock of TIM2 is stopped and the output is disabled when the core is halted