Siemens ERTEC 200P, Руководство пользователя

Страница: 460 / 501

Copyright © Siemens AG 2016. All rights reserved 460 ERTEC 200P-2 Manual
Technical data subject to change Version 1.0
The following figure shows the timing, when the External Host initiates a Write Access :
XHIF_XCS_M/R_I
XHIF_XWR_I
XHIF_A_I(19:0)
XHIF_SEG_I(2:0)
XHIF_XRDY_O /
XHIF_XRDY_OE
XHIF_D_I(31:0)
t
CSWS
t
AWS
t
WCSH
t
WR
t
WAH
t
RAP
t
WRT
t
WDV
t
RTW
t
WDH
t
WDE
Trigger off access
Parameter Description Min Max
t
CSWS
chip select asserted to write pulse asserted delay 0.8 ns
1)
t
AWS
address valid to write pulse asserted setup time 1.9 ns
t
WRT
write pulse asserted to ready deasserted delay 4.0 ns 11.2
ns
t
WDE
write pulse asserted to data enable setup 0 ns t.b.d
ns
3)
t
WDV
write pulse asserted to data valid delay 15.7
ns
t
RAP
ready active pulse width 6.1 ns 10.1
ns
t
WCSH
write pulse deasserted to chip select deasserted
delay 1.7 ns
2)
t
WAH
address valid to write pulse deasserted hold time 1.6 ns
t
RTW
ready asserted to write pulse deasserted delay 0 ns
t
WDH
data valid/enabled to read pulse deasserted hold
time 1.8 ns
2)
t
WR
write recovery time 10.9 ns
Based on
Tc = 8 ns (AHB Clock = 125 MHz);
Load-value for Timing = 20pF
Buffer Driverstrength = 9mA
IO-Voltage = 3,3V
1)
If t
CSWS
< 0, t
AWS
, t
WRT
and t
WDE
are related to the falling edge of XHIF_XCS
2)
If t
WCSH
< 0, t
WAH
and t
WDH
are related to the rising edge of XHIF_XCS
3)
t
WDE
may get any value, as long as it is assured, that there is 1 idle cycle (of the XHIF clock period) guaranteed be-
tween the end of the preceding access and the start of the current access (indicated by the falling edge of XCS/XWR).
Within this idle cycle no access is allowed at all.