Copyright © Siemens AG 2016. All rights reserved
389
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
1: Reads LOC_IO47 Out
16 GPIO80_IN_MUX
xh
r w
0: Reads GPIO80 pad
1: Reads LOC_IO48 Out
17 GPIO81_IN_MUX
xh
r w
0: Reads GPIO81 pad
1: Reads LOC_IO49 Out
18 GPIO82_IN_MUX
xh
r w
0: Reads GPIO82 pad
1: Reads LOC_IO50 Out
19 GPIO83_IN_MUX
xh
r w
0: Reads GPIO83 pad
1: Reads LOC_IO51 Out
20 GPIO84_IN_MUX
xh
r w
0: Reads GPIO84 pad
1: Reads LOC_IO52 Out
21 GPIO85_IN_MUX
xh
r w
0: Reads GPIO85 pad
1: Reads LOC_IO53 Out
22 GPIO86_IN_MUX
xh
r w
0: Reads GPIO86 pad
1: Reads LOC_IO54 Out
23 GPIO87_IN_MUX
xh
r w
0: Reads GPIO87 pad
1: Reads LOC_IO55 Out
24 GPIO88_IN_MUX
xh
r w
0: Reads GPIO88 pad
1: Reads LOC_IO56 Out
25 GPIO89_IN_MUX
xh
r w
0: Reads GPIO89 pad
1: Reads LOC_IO57 Out
26 GPIO90_IN_MUX
xh
r w
0: Reads GPIO90 pad
1: Reads LOC_IO58 Out
27 GPIO91_IN_MUX
xh
r w
0: Reads GPIO91 pad
1: Reads LOC_IO59 Out
28 GPIO92_IN_MUX
xh
r w
0: Reads GPIO92 pad
1: Reads LOC_IO60 Out
29 GPIO93_IN_MUX
xh
r w
0: Reads GPIO93 pad
1: Reads LOC_IO61 Out
30 GPIO94_IN_MUX
xh
r w
0: Reads GPIO94 pad
1: Reads LOC_IO62 Out
31 GPIO95_IN_MUX
xh
r w
0: Reads GPIO95 pad
1: Reads LOC_IO63 Out
Register:
CCR_I2C
Address: 50h
Bits:
31dt0
Reset value: 7Ch
Attribu-
tes:
r
w
Description:
Clock Control register for the I2C_3 interface divider value
for determining the bit rate.
Содержание ERTEC 200P
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