Siemens ERTEC 200P, Руководство пользователя

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Copyright © Siemens AG 2016. All rights reserved 272 ERTEC 200P-2 Manual
Technical data subject to change Version 1.0
The TIMER_TOP module has a clock divider for providing a clock for external modules,
which is symmetrical with the input clock CLK_TIMT. The clock divider is 8 bits wide
(NUM_OF_CLKDIV_BITS). The clock divider value is set by writing on the bits in the
CLOCK_DIVIDER_REG register. A writing of the register CLOCK_DIVIDER_REG loads
the clock divider with the clock divider value. The current value of the clock divider is
nonreadable.
The clock divider output CLK_OUT is ’0’ as long as the clock dividing has not been acti-
vated.
The clock dividing is activated by setting the CLK_DIV_EN bit to ’1’ and by writing the
clock divider value CLOCK_DIVIDER_VALUE with a value unequal to 0 (in the register
CLOCK_DIVIDER_REG).
When clock dividing is active, the following applies:
The clock divider output CLK_OUT is ’0’ as long as the clock divider has a value
smaller than CLKDIV_VALUE/2, otherwise ’1’.
The divided clock CLK_OUT is symmetrical if the clock divider value is odd-numbered.
If the current value of the clock divider is ‘0’, the clock divider is loaded with the value
of the bits CLOCK_DIVIDER_VALUE.
When clock dividing is enabled, the clock divider value CLOCK_DIVIDER_VALUE must
not be changed. Before changing the clock divider value CLOCK_DIVIDER_VALUE the
clock dividing must be disabled by setting Clock Divider Enable CLK_DIV_EN to 0.
Attention: Writing a new clock divider value CLOCK_DIVIDER_VALUE may have the
effect that CLK_OUT runs with a wrong clock period once.
The clock divider is implemented as a down-counter which counts down cyclically from
the clock divider value CLKDIV_VALUE.
The clock divider divides the frequency of input clock CLK_TIMT by the factor 1 /
(CLKDI1). Exception: A clock divider value of 0 supplies CLK_OUT=0.
Possible values for the clock divider value CLKDIV_VALUE: ’0’ to ’2^8-1’. At 125 MHz
there are therefore output frequencies of 125 MHz / 2^8 - 125 MHz / 2 possible.
Timer cascading:
The TIMER modules are cascadable under certain conditions. The items stated under
“Cascading of TIMER modules” have to be taken into account for that.