Rohde & Schwarz 1094.0006.50, Руководство по эксплуатации

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CTS55 Remote Control
1094.0006.55 11.17 E-5
11.8 Status Reporting System
The status reporting system (cf. Fig. 11-4) stores all information on the present operating state of the
instrument and on errors which have occurred. This information is stored in the status registers and in
the error queue. The status registers and the error queue can be queried via the remote-control
interface.
The information is of a hierarchical structure. The register status byte (STB) defined in IEEE 488.2 and
its associated mask register service request enable (SRE) form the uppermost level. The STB receives
its information from the standard event status register (ESR) which is also defined in IEEE 488.2 with
the associated mask register standard event status enable (ESE) and registers STATus:OPERation and
STATus:QUEStionable which are defined by SCPI and contain detailed information on the instrument.
The IST flag ("Individual STatus") and the parallel poll enable register (PPE) allocated to it are also part
of the status reporting system. The IST flag, like the SRQ, combines the entire instrument status in a
single bit. The PPE fulfills an analog function for the IST flag as the SRE for the service request.
The output buffer contains the messages the instrument returns to the controller. It is not part of the
status reporting system but determines the value of the MAV bit in the STB and thus is represented in
Fig. 11-4.
11.8.1 Structure of an SCPI Status Register
Each SCPI register consists of 5 parts which each have a width of 16 bits and have different functions
(cf. Fig. 11-3). The individual bits are independent of each other, i.e. each hardware status is assigned a
bit number which is valid for all five parts. For example, bit 3 of the STATus:OPERation register is
assigned to the hardware status "wait for trigger" in all five parts. Bit 15 (the most significant bit) is set to
zero for all parts. Thus the contents of the register parts can be processed by the controller as positive
integer.
15 14 13 12 PTRansition part 3 2 1 0
15 14 13 12 EVENT part 3 2 1 0
15 14 13 12 ENABle part 3 2 1 0
& & & & & & & & & & & & & & & &
to higher-order register
Sum bit
& = logisch AND
= logisch OR
of all bits
+
+
15 14 13 12 NTRansition part 3 2 1 0
15 14 13 12 CONDition part 3 2 1 0
Fig. 11-3 The status-register model