![background image](http://html1.mh-extra.com/html/omron/cp1l-cpu-unit-03-2009/cp1l-cpu-unit-03-2009_operation-manual_742084350.webp)
316
Inverter Positioning
Section 5-3
Read/Write Area
Note
Present Values of High-speed Counter and Pulse Outputs
The present value of the high-speed counter when inverter positioning is used
is stored in the same memory location as for normal high-speed counter appli-
cation. This value can be used as the present value of feedback pulses from
the encoder, i.e., as the absolute position of inverter positioning. Target value
and range comparisons for high-speed counters are also valid.
The present value of the pulse output (A276/A277 or A278/A279), i.e., the
pulse output value to the error counter, is an absolute position if an absolute
coordinate system is specified and is a relative position if a relative coordinate
system is specified.
A278 00 to 15 Lower 4 digits of the
present value of the
internal pulse output
(absolute value for
absolute coordi-
nates)
8000 0000 to 7FFF
FFFF hex
(
−
2,147,483,648 to
2,147,483,647)
Contains absolute movement value
from the internal pulse origin when
pulses are output to error counter.
Cleared to zero at following times:
• When power to CPU Unit is turned ON
• When operation is started
Updated at following times:
• Cyclically on error counter cycle
This value can be
used to monitor the
present value of
the internal pulse
output as an abso-
lute value when
using absolute
coordinates.
A279 00 to 15 Upper 4 digits of the
present value of the
internal pulse output
(absolute value for
absolute coordi-
nates)
Word
Bits
Function
Data range
Refresh timing
Application
examples
Word
Bits
Function
Data range
Refresh
timing
Application
A562
00
Inverter
positioning 0
Error Counter
Reset Bit
Turned ON: Error counter 0
present value (A22) reset and
Error Counter Error Flag cleared.
---
Turn ON this bit to
clear the error
counter error status.
01
Error Counter
Disable Bit
While ON: Error counter value
held.
---
Turn ON this bit, for
example, to disable
accumulating
pulses in the error
counter when stop-
ping positioning and
moving the motor
shaft manually.
02 to 15 Not used.
A563
00
Inverter
positioning 1
Error Counter
Reset Bit
Turned ON: Error counter 0
present value (A32) reset and
Error Counter Error Flag cleared.
---
Turn ON this bit to
clear the error
counter error status.
01
Error Counter
Disable Bit
While ON: Error counter value
held.
---
Turn ON this bit, for
example, to disable
accumulating
pulses in the error
counter when stop-
ping positioning and
moving the motor
shaft manually.
02 to 15 Not used.
Содержание CP1L CPU UNIT - 03-2009
Страница 1: ...Cat No W462 E1 06 CP1L CPU Unit SYSMAC CP Series CP1L L_0D_ CP1L M_0D_ OPERATION MANUAL...
Страница 2: ......
Страница 4: ...iv...
Страница 10: ...x...
Страница 22: ...xxii...
Страница 34: ...xxxiv Conformance to EC Directives 6...
Страница 70: ...36 Function Blocks Section 1 5...
Страница 584: ...550 Trouble Shooting Section 8 7...
Страница 627: ...593 Sample Application Section 9 12 Network Settings Network Tab Network Settings Driver Tab...
Страница 630: ...596 Sample Application Section 9 12...
Страница 654: ...620 Troubleshooting Unit Errors Section 11 4...
Страница 662: ...628 Replacing User serviceable Parts Section 12 2...
Страница 668: ...634 Standard Models Appendix A...
Страница 698: ...664 Auxiliary Area Allocations by Function Appendix C...
Страница 746: ...712 Auxiliary Area Allocations by Address Appendix D...
Страница 773: ...739 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 774: ...740 Connections to Serial Communications Option Boards Appendix F...
Страница 806: ...772 Index...
Страница 808: ...774 Revision History...