Omron CP1L CPU UNIT - 03-2009, Руководство по эксплуатации

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Index Registers Section 4-11
4-11-1 Using Index Registers
Processing of multiple (identical) instructions such as consecutive addresses
for table data can be merged into one instruction by combining repetitive pro-
cessing (e.g., FOR(513) and NEXT(514)instructions) with indirect addressing
using Index Registers, thereby simplifying programming.
The Index operation uses the following procedure.
1. PLC memory addresses for the addresses in the Index Registers are
stored using a MOVR instruction.
2. Operation is then executed by indirectly addressing Index Registers to the
operand for Instruction A.
3. The addresses are moved using processing such as adding, subtracting,
incrementing, or decrementing the Index Register (see note).
4. Steps 2 and 3 are processed repeatedly until the conditions are met.
Note Adding, subtracting incrementing, or decrementing for the Index
Register is performed using one of the following methods.
• Each Type of Indirect Addressing for Index Registers:
Auto-increment (,IR
@
+ or ,IR
@
++), auto-decrement (,-IR
@
or ,--IR
@
),
constant offset (constant ,IR
@
), and DR offset (DR
@
,IR
@
) for Index
Registers
• Instructions for Direct Addressing of Index Registers:
DOUBLE SIGNED BINARY ADD WITHOUT CARRY (+L), DOUBLE
SIGNED BINARY SUBTRACT WITHOUT CARRY (-L), DOUBLE IN-
CREMENT BINARY (++L), DOUBLE DECREMENT BINARY (--L)
Example:
If, for example, instruction A above is a comparison instruction, table data
could be read from start to the end of the table to compare all of the data with
a specific value. In this way, blocks of user-defined processing can be freely
created depending by applying Index Registers.
IR0
,IR0
Instruction execution
repeatedly incrementing
IR0 by 1
Instruction
Indirect
addressing
Table data
Instruction A
Instruction A m+1
Instruction A m+n
MOVR m IR0
The PLC memory address
of address m is stored in IR0.
Repeated execution,
e.g., loop for
FOR or NEXT.
Instruction A ,IR0+