205
Pulse Outputs
Section 5-2
■
Setting Functions Using Instructions and PLC Setup
CPU Units with 10 I/O Points
CPU Units with 14 I/O Points
Address
Default setting
High-speed counter operation settings
Origin searches
Word
Bit
Single-phase
(increment pulse input)
Two-phase (differential
phases x4, up/down, or
pulse/direction)
Origin searches
enabled for pulse
outputs 0
CIO 0
00
Normal input 0
Counter 0, increment input
Counter 0, A phase, up, or
count input
---
01
Normal input 1
Counter 1, increment input
Counter 0, B phase, down,
or direction input
---
02
Normal input 2
Counter 2, increment input
Counter 1, A phase, up, or
count input
---
03
Normal input 3
Counter 3, increment input
Counter 1, B phase, down,
or direction input
Pulse output 0: Origin
proximity input signal
04
Normal input 4
Counter 0, phase-Z/reset
input
Counter 0, phase-Z reset
input
---
05
Normal input 5
Counter 1, phase-Z reset
input
Counter 1, phase-Z reset
input
Pulse output 0: Origin
input signal
Input terminal
block
Default setting
High-speed counter operation settings
Origin searches
Word
Bit
Single-phase
(increment pulse input)
Two-phase (differential
phases x4, up/down, or
pulse/direction)
Origin searches
enabled for pulse
outputs 0 and 1
CIO 0
00
Normal input 0
High-speed counter 0
(Increment)
High-speed counter 0
(Phase A, Increment, or
Count input)
---
01
Normal input 1
High-speed counter 1
(Increment)
High-speed counter 0
(Phase B, Decrement, or
Direction input)
---
02
Normal input 2
High-speed counter 2
(Increment)
High-speed counter 1
(Phase A, Increment, or
Count input)
Pulse output 0:
Origin proximity input
signal
03
Normal input 3
High-speed counter 3
(Increment)
High-speed counter 1
(Phase B, Decrement, or
Direction input)
Pulse output 1:
Origin proximity input
signal
04
Normal input 4
High-speed counter 0
(Phase Z or reset input)
High-speed counter 0
(Phase Z or reset input)
---
05
Normal input 5
High-speed counter 1
(Phase Z or reset input)
High-speed counter 1
(Phase Z or reset input)
---
06
Normal input 6
High-speed counter 2
(Phase Z or reset input)
---
Pulse output 0:
Origin input signal
07
Normal input 7
High-speed counter 3
(Phase Z or reset input)
---
Pulse output 1:
Origin input signal
Содержание CP1L CPU UNIT - 03-2009
Страница 1: ...Cat No W462 E1 06 CP1L CPU Unit SYSMAC CP Series CP1L L_0D_ CP1L M_0D_ OPERATION MANUAL...
Страница 2: ......
Страница 4: ...iv...
Страница 10: ...x...
Страница 22: ...xxii...
Страница 34: ...xxxiv Conformance to EC Directives 6...
Страница 70: ...36 Function Blocks Section 1 5...
Страница 584: ...550 Trouble Shooting Section 8 7...
Страница 627: ...593 Sample Application Section 9 12 Network Settings Network Tab Network Settings Driver Tab...
Страница 630: ...596 Sample Application Section 9 12...
Страница 654: ...620 Troubleshooting Unit Errors Section 11 4...
Страница 662: ...628 Replacing User serviceable Parts Section 12 2...
Страница 668: ...634 Standard Models Appendix A...
Страница 698: ...664 Auxiliary Area Allocations by Function Appendix C...
Страница 746: ...712 Auxiliary Area Allocations by Address Appendix D...
Страница 773: ...739 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 774: ...740 Connections to Serial Communications Option Boards Appendix F...
Страница 806: ...772 Index...
Страница 808: ...774 Revision History...