![background image](http://html1.mh-extra.com/html/omron/cp1l-cpu-unit-03-2009/cp1l-cpu-unit-03-2009_operation-manual_742084701.webp)
667
Auxiliary Area Allocations by Address
Appendix D
A26
04
Error Counter
Error Flag 0
This flag turns ON when an error
occurs in the error counter for
inverter positioning 0.
ON: Error
counter error
OFF: No error
---
Cleared
When
pulse out-
put to error
counter is
stopped
and abso-
lute value
of error
counter
present
value is
greater
than or
equal to
error
counter
error
detection
value
---
05
Error Counter
Pulse Output
Flag 0
This flag is ON while pulses are
being output to the output counter for
inverter positioning 0.
ON: Pulses
being output
OFF: Pulse
output
stopped
---
Cleared
When
pulse out-
put to error
counter 0
is started
---
06
Error Counter
Pulse Output
Acceleration/
Deceleration
Flag 0
This flag is ON while pulse output to
the output counter for inverter posi-
tioning 0 is accelerating or decelerat-
ing.
ON: Pulse
output to the
error counter
is accelerat-
ing or decel-
erating (i.e.,
the fre-
quency is
changing)
OFF: Pulse
output to the
error counter
is constant
---
Cleared
When
pulse out-
put fre-
quency to
error
counter is
changed
by ACC or
PLS2
instruction
---
07
Error Counter
Alarm Flag 0
This flag turns ON when an alarm
occurs in the error counter for
inverter positioning 0.
ON: Error
counter alarm
OFF: No error
counter alarm
---
Cleared
When
pulse out-
put to error
counter is
stopped
and abso-
lute value
of error
counter
present
value is
greater
than or
equal to
error
counter
alarm
detection
value
---
15
Inverter Posi-
tioning Output
Value Sign
Flag 0
This flag is ON when the inverter
positioning 0 output value is positive
and is OFF when it is negative.
ON: Positive
value
OFF: Nega-
tive value
---
Cleared
When
signed out-
put value is
between
0000 0000
and 7FFF
FFFF hex
---
A28
and
A29
---
Present Value
of Pulse Out-
put to Inverter
0, Relative
Value
These words contain the relative
value of the internal pulse output
when pulses are being output to the
error counter for inverter positioning
0.
Data range: 8000 0000 to 7FFF
FFFF hex (
−
2,147,483,648 to
2,147,483,647)
---
---
Cleared
Every error
counter 0
cycle
---
Address
Name
Function
Settings
Status
after
mode
change
Status
at star-
tup
Write
timing
Related
flags, set-
tings
Words
Bits
Содержание CP1L CPU UNIT - 03-2009
Страница 1: ...Cat No W462 E1 06 CP1L CPU Unit SYSMAC CP Series CP1L L_0D_ CP1L M_0D_ OPERATION MANUAL...
Страница 2: ......
Страница 4: ...iv...
Страница 10: ...x...
Страница 22: ...xxii...
Страница 34: ...xxxiv Conformance to EC Directives 6...
Страница 70: ...36 Function Blocks Section 1 5...
Страница 584: ...550 Trouble Shooting Section 8 7...
Страница 627: ...593 Sample Application Section 9 12 Network Settings Network Tab Network Settings Driver Tab...
Страница 630: ...596 Sample Application Section 9 12...
Страница 654: ...620 Troubleshooting Unit Errors Section 11 4...
Страница 662: ...628 Replacing User serviceable Parts Section 12 2...
Страница 668: ...634 Standard Models Appendix A...
Страница 698: ...664 Auxiliary Area Allocations by Function Appendix C...
Страница 746: ...712 Auxiliary Area Allocations by Address Appendix D...
Страница 773: ...739 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 774: ...740 Connections to Serial Communications Option Boards Appendix F...
Страница 806: ...772 Index...
Страница 808: ...774 Revision History...