Omron CP1L CPU UNIT - 03-2009, Руководство по эксплуатации

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Auxiliary Area Allocations by Address Appendix D
A531 A531.08 High-speed
Counter 0
Gate Bit
When a counter's Gate Bit is ON, the
counter's PV will not be changed
even if pulse inputs are received for
the counter.
When the bit is turned OFF again,
counting will restart and the high-
speed counter's PV will be refreshed.
When the reset method is set to
Phase-Z Software reset, the
Gate Bit is disabled while the corre-
sponding Reset Bit (A531.00 or
A531.01) is ON. --- Retained Cleared --- ---
A531.09 High-speed
Counter 1
Gate Bit
--- Retained Cleared --- ---
A532 All Interrupt
Counter 0
Counter SV Used for interrupt input 0 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
140 will start when interrupt counter
0 has counted this number of pulses.
Retained when operation starts. --- Retained Retained --- ---
A533 All Interrupt
Counter 1
Counter SV Used for interrupt input 1 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
141 will start when interrupt counter
1 has counted this number of pulses. --- Retained Retained --- ---
A534 All Interrupt
Counter 2
Counter SV Used for interrupt input 2 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
142 will start when interrupt counter
2 has counted this number of pulses. --- Retained Retained --- ---
A535 All Interrupt
Counter 3
Counter SV Used for interrupt input 3 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
143 will start when interrupt counter
3 has counted this number of pulses. --- Retained Retained --- ---
A536 All Interrupt
Counter 0
Counter PV These words contain the interrupt
counter PVs for interrupt inputs oper-
ating in counter mode.
In increment mode, the counter PV
starts incrementing from 0. When the
counter PV reaches the counter SV,
the PV is automatically reset to 0.
In decrement mode, the counter PV
starts decrementing from the counter
SV. When the counter PV reaches
the 0, the PV is automatically reset to
the SV.
Cleared when operation starts. --- --- Retained Refresh-
ed when
interrupt
is gener-
ated.
Refresh-
ed when
INI(880)
instruc-
tion is
executed. ---
A537 All Interrupt
Counter 1
Counter PV --- --- ---
A538 All Interrupt
Counter 2
Counter PV --- --- ---
A539 All Interrupt
Counter 3
Counter PV --- --- ---
A540 A540.00 Pulse Out-
put 0 Reset
Bit
The pulse output 0 PV (contained in
A276 and A277) will be cleared when
this bit is turned ON. --- Retained Cleared --- A276 and
A277
A540.08 Pulse Out-
put 0 CW
Limit Input
Signal Flag
This is the CW limit input signal for
pulse output 0, which is used in the
origin search. To use this signal,
write the input from the actual sensor
as an input condition in the ladder
program and output the result to this
flag. --- Retained Cleared --- ---
A540.09 Pulse Out-
put 0 CCW
Limit Input
Signal Flag
This is the CCW limit input signal for
pulse output 0, which is used in the
origin search. To use this signal,
write the input from the actual sensor
as an input condition in the ladder
program and output the result to this
flag. --- Retained Cleared --- ---
Addresses Name Function Settings Status
after
mode
change
Status at
startup
Write
timing
Related
Flags,
Settings
Word Bits